1. Field of the Invention
The present invention relates to a semiconductor device including a P-N column layer and a method for manufacturing the same.
2. Description of Related Art
Recently, in a field of power semiconductor device, a vertical type super junction semiconductor device (referred also to herein as SJ-MOS) has been known as a semiconductor device that may be capable of having both a high breakdown voltage and a low on-state resistance. The SJ-MOS includes a P-N column layer, which functions as a super junction (SJ) and provides a drift layer. An SJ-MOS like the above devices is disclosed in, for example, Japanese Unexamined Patent Application Publication Number 2002-76339 corresponding to U.S. Pat. No. 6,621,132.
Japanese Patent Number 3485081 (corresponding to U.S. Pat. No. 6,495,294) and Japanese Unexamined Patent Application Publication Number 2004-273742 (corresponding to U.S. Pat. No. 7,029,977) show a method for manufacturing a P-N column layer like the above P-N column layer, the method including: forming multiple trenches in an N conductivity type epitaxial layer; and forming a trench filling epitaxial layer having a P conductivity type in each trench. According to the above method, the trench filling epitaxial layer is formed, for example, through an anisotropic growth from a bottom of each trench by Low Pressure Chemical Vapor Deposition (LP-CVD) under a condition of simultaneously flowing silicon source gas (e.g., SiH2Cl2) and halide gas (e.g., HCl). The halide gas functions as etching gas.
The above manufacturing method, however, may be difficult to stably provide a semiconductor device including a P-N column layer having columns with high aspect ratios.